module reg_file_sm (
                    //<interface> Bram Ctrl
                    input         bram_rst_a,

                    input         bram_clk_a,
                    input         bram_en_a,
                    input [3:0]   bram_we_a, //BRAM Port A (write port) write enable signal. Active High. Byte wise signal to width of block RAM
                    input [12:0]  bram_addr_a,
                    input [31:0]  bram_wrdata_a,
                    output [31:0] bram_rddata_a,

                    output [31:0] config_readback_ctrl_r  ,
                    output [31:0] config_readback_len_r   ,
                    input  [31:0] config_readback_status 

 ) ;
   //////////////////////////////////////////////////////////////////
  //parameter of selectmap_master registers
   //////////////////////////////////////////////////////////////////
   
`define REG_ADDR_BASE_0 'h0
`define REG_ADDR_BASE_1 'h4
`define REG_ADDR_BASE_2 'h8  




   reg [31:0]                  config_readback_ctrl_r  ;
   reg [31:0]                  config_readback_len_r   ;
   reg [31:0]                  config_readback_status_r ;
   

   //reg for input shift
   reg                         bram_en_a_r;
   reg [3:0]                   bram_we_a_r;
   reg [12:0]                  bram_addr_a_r;
   reg [31:0]                  bram_wrdata_a_r;
   //reg for output
   reg [31:0]                  bram_rddata_a_r;

   //<operation> <blocking> <write> <data> bram_rddata_a of <interface> Bram Ctrl <is>
   assign bram_rddata_a = bram_rddata_a_r;

   //<operation> <shift-register> of <interface> Bram Ctrl <is>
   always@(posedge bram_clk_a, negedge bram_rst_a)begin
      if(bram_rst_a)begin //for reset
         bram_en_a_r <= 'h0;
         bram_we_a_r <= 'h0;
         bram_addr_a_r <= 'h0;
         bram_wrdata_a_r <= 'h0;
      end
      else begin
         bram_en_a_r <= bram_en_a;
         bram_we_a_r <= bram_we_a;
         bram_addr_a_r <= bram_addr_a;
         bram_wrdata_a_r <= bram_wrdata_a;
      end
   end // always@ (posedge bram_clk_a, negedge bram_rst_a)

   //<function> <map> <read-address> of registers <is>
   always@(posedge bram_clk_a)
     begin
        //<operation> <map> <read-addres>  
        // of <registers> config_readback_ctrl_r, config_readback_len_r, config_readback_status_r <is>
        case(bram_addr_a[12:0])
          `REG_ADDR_BASE_0:
            bram_rddata_a_r <= config_readback_ctrl_r;
          `REG_ADDR_BASE_1:
            bram_rddata_a_r <= config_readback_len_r;
          `REG_ADDR_BASE_2:
            bram_rddata_a_r <= config_readback_status_r;
          
          default: 
            bram_rddata_a_r <= 'hx;
        endcase
     end // always@ (posedge bram_clk_a)

   //<function> <map> <write-address> of registers <is>
   always@(posedge bram_clk_a, negedge bram_rst_a)begin
      if(bram_rst_a)begin //for reset       
         config_readback_ctrl_r   <= 32'h0;
         config_readback_len_r    <= 32'h0;
      end
      else begin
         //<operation> <map> <write-addres> 
         // of <registers> config_readback_ctrl_r config_readback_len_r <is>
                
         if(bram_en_a_r==1'b1 && bram_we_a_r == 4'hf)begin
            case(bram_addr_a_r)
              
              `REG_ADDR_BASE_0:
                config_readback_ctrl_r <= bram_rddata_a_r;
              `REG_ADDR_BASE_1:
                config_readback_len_r <= bram_rddata_a_r;
            endcase // case (bram_addr_a_r)
         end
         
      end
   end

   //<operation> <refresh> <register> config_readback_status_r <is>
   always@(posedge bram_clk_a, negedge bram_rst_a)begin
      if(bram_rst_a)begin //for reset
         config_readback_status_r <= 32'h0;
      end
      else begin
         config_readback_status_r <= config_readback_status;
      end
   end
         

   
endmodule // reg_file_sm
